{"created":"2023-06-20T16:34:48.682252+00:00","id":4064,"links":{},"metadata":{"_buckets":{"deposit":"4cdc84f1-fb8c-45c3-a1ec-7d42e1eae9af"},"_deposit":{"created_by":3,"id":"4064","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"4064"},"status":"published"},"_oai":{"id":"oai:kindai.repo.nii.ac.jp:00004064","sets":["14:2794:2816","21:2796:2817"]},"author_link":["5295"],"item_5_biblio_info_21":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"1","bibliographicPageStart":"1","bibliographic_titles":[{"bibliographic_title":"近畿大学研究成果シーズ"},{"bibliographic_title":"Seeds Kinki University","bibliographic_titleLang":"en"}]}]},"item_5_description_33":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"[概要]静的な基板バイアス［V_<DD>' (＞V_<DD>),  V_<SS>' (＜_V_<SS>)］を印加して, ソース端子が電源電圧V_<DD> 及び接地電圧V_<SS>に直接接続する全てのプルアップ／プルダウン･トランジスタを高い閾値電圧にし, 低い閾値電圧を持つPMOS トランジスタの基板であるn ウエルを作成しない, 静的基板バイアス印加ドミノCMOS（SSDCMOS）集積回路を開発しました。通常のn ウエルを無くすることにより, 大幅に回路面積が減ります。またそのトランジスタ幅を負荷状況にあわせて容易に変え得るような標準セルのレイアウト構造を考案し, 低消費電力なCMOS 集積回路の標準セルを実現しました。","subitem_description_type":"Abstract"}]},"item_5_description_36":{"attribute_name":"内容記述","attribute_value_mlt":[{"subitem_description":"分野：デバイス,　特許出願： 特願 平成11-350529","subitem_description_type":"Other"}]},"item_5_description_37":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"subitem_description":"Others","subitem_description_type":"Other"}]},"item_5_description_41":{"attribute_name":"フォーマット","attribute_value_mlt":[{"subitem_description":"application/pdf","subitem_description_type":"Other"}]},"item_5_publisher_14":{"attribute_name":"出版者 名前","attribute_value_mlt":[{"subitem_publisher":"近畿大学リエゾンセンター"}]},"item_5_text_8":{"attribute_name":"著者 所属","attribute_value_mlt":[{"subitem_text_value":"近畿大学生物理工学部 電子システム情報工学科"}]},"item_5_text_9":{"attribute_name":"著者所属(翻訳)","attribute_value_mlt":[{"subitem_text_value":"Kinki University"}]},"item_5_textarea_42":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_textarea_value":"SEEDS_kindai_K-001"}]},"item_5_version_type_12":{"attribute_name":"版","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"秋濃,  俊郎"}],"nameIdentifiers":[{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2016-02-18"}],"displaytype":"detail","filename":"SEEDS_kindai_K-001.pdf","filesize":[{"value":"149.0 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"SEEDS_kindai_K-001.pdf","url":"https://kindai.repo.nii.ac.jp/record/4064/files/SEEDS_kindai_K-001.pdf"},"version_id":"425f373a-0242-446a-b27f-0001cf9952d8"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"CMOS集積回路","subitem_subject_scheme":"Other"},{"subitem_subject":"標準セル","subitem_subject_scheme":"Other"},{"subitem_subject":"基板バイアス","subitem_subject_scheme":"Other"},{"subitem_subject":"閾値電圧","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"other","resourceuri":"http://purl.org/coar/resource_type/c_1843"}]},"item_title":"CMOS集積回路のトランジスタ幅が可変となる標準セル構造の研究","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"CMOS集積回路のトランジスタ幅が可変となる標準セル構造の研究"}]},"item_type_id":"5","owner":"3","path":["2816","2817"],"pubdate":{"attribute_name":"公開日","attribute_value":"2012-10-24"},"publish_date":"2012-10-24","publish_status":"0","recid":"4064","relation_version_is_last":true,"title":["CMOS集積回路のトランジスタ幅が可変となる標準セル構造の研究"],"weko_creator_id":"3","weko_shared_id":-1},"updated":"2023-06-21T01:18:47.045266+00:00"}